Signoff (electronic design automation): Difference between revisions

Revision as of 02:20, 31 August 2012

Revision as of 05:58, 10 January 2013

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== Tools ==

A small subset of tools are classified as "golden" or signoff-quality. Categorizing a tool as signoff-quality without vendor-bias is a matter of trial and error, since the accuracy of the tool can only be determined after the design has been fabricated. So, one of the metrics that is in use (and often touted by the tool manufacturer/vendor) is the number of successful tapeouts enabled by the tool in question. It has been argued that this metric is insufficient, ill-defined, and irrelevant for certain tools, especially tools that play only a part in the full flow.<ref>[http://www.eetimes.com/op/showArticle.jhtml?articleID=18305399 EETimes.com: Vendors should count silicon, not tapeout wins]</ref>.

While vendors often embellish the ease of end-to-end (typically [[Register transfer level|RTL]] to [[GDSII|GDS]] for [[ASIC]]s, and RTL to [[timing closure]] for [[FPGA]]s) execution through their respective tool suite, most semiconductor design companies use a combination of tools from various vendors (often called "[[best of breed]]" tools) in order to minimize correlation errors pre- and post-silicon.<ref>DeepChip - [http://www.deepchip.com/items/snug07-09.html SNUG survey of physical verification tools].</ref>. Since independent tool evaluation is expensive (single licenses for design tools from major vendors like [[Synopsys]] and [[Cadence Design Systems|Cadence]] may cost tens or hundreds of thousands of dollars) and a risky proposition (if the failed evaluation is done on a production design, resulting in a [[time to market]] delay), it is feasible only for the largest design companies (like [[Intel]], [[International Business Machines|IBM]], [[Freescale Semiconductor|Freescale]], and [[Texas Instruments|TI]]). As a [[value add]], several semiconductor foundries now provide pre-evaluated reference/recommended methodologies (sometimes referred to as "RM" flows) which includes a list of recommended tools, versions, and scripts to move data from one tool to another and automate the entire process.<ref>[http://www.eetimes.com/showArticle.jhtml?articleID=216900259&printable=true TSMC's sign-off flow]</ref>.

This list of vendors and tools is meant to be representative and is not exhaustive:

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* Signal integrity analysis - [http://w2.cadence.com/datasheets/3073E_CeltIC_DS_Fnl.pdf Cadence CeltIC] (crosstalk noise), [http://www.synopsys.com/Tools/Implementation/SignOff/Pages/PrimeTime.aspx Synopsys PrimeTime SI] (crosstalk delay/noise), [http://www.extreme-da.com/Gold_Time_Suite.html Extreme-DA GoldTime SI] (crosstalk delay/noise)

* Static timing analysis - [http://www.synopsys.com/Tools/Implementation/SignOff/Pages/PrimeTime.aspx Synopsys PrimeTime], [http://www.magma-da.com/products-solutions/verification/quartzssta.aspx Magma Quartz SSTA], [http://www.cadence.com/products/di/ets/pages/default.aspx Cadence ETS], [http://www.extreme-da.com/Gold_Time_Suite.html Extreme-DA GoldTime]

== References ==