XCore Architecture: Difference between revisions

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Revision as of 07:54, 11 January 2013

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The '''XCore XS1''' is a 32-bit RISC microprocessor architecture designed by [[XMOS]]. The architecture is designed to be used in [[multi-core processor]]s for [[embedded system|embedded systems]]s. Each XS1 core executes up to eight concurrent threads, each thread having its own register set, and the architecture directly supports inter-thread and inter-core communication and various forms of thread scheduling.<ref>{{cite web

|title=XMOS XS1 Architecture Brief

|format=PDF |date=07-12-2011

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Processors with this architecture include the [[XCore XS1-G4]] and [[XCore XS1-L1]].

==Architecture==

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The status register contains various mode bits, but the processor does ''not'' have the standard ALU result flags like [[Carry flag|carry]], [[Zero flag|zero]], [[Negative flag|negative]] or [[Overflow flag|overflow]]. Add and subtract with carry instructions exist, but specify 5 operand registers: 2 inputs and input carry, and one output and output carry.

===Instruction encoding===

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(A few instructions use the register ''c'' field value 0–11 as a small immediate constant, or use it to select one of 12 convenient bit-shift

constants 0–8, 16, 24, or 32.)

Less frequently used instructions are encoded in 32 bits. 32-bit instructions allow 16-or 20-bit immediate operands (such as far branches), up to 6 register operands (for example long multiply which has 4 source and two destination operands) and additional opcode space for rarely used instructions.

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==Sequential programming model==

Each thread has access to 12 general purpose registers R0...R11. In addition there are 4 special purpose registers the SP, LR (Link register - stores the return address), CP (constant pool, points to a part of memory that stores constants) and DP (data pool - points to global variables). In addition to those 16 there are another 9 registers that store the PC, kernel PC, Exception type, Exception data, and saved copies of all those in case of an exception or interrupt.<ref>{{cite web

|title=XMOS XS1 Architecture |format=PDF

|url=https://www.xmos.com/published/xmos-xs1-architecture

|author=David May

|publisher=[[XMOS]]}} (Free registration required)</ref>.

The instruction set is a [[Load-store architecture|load-store]] instruction set.

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allocated threads by setting their initial register values.

Communication between threads is performed using channels that provide full-duplex data transfer between channel-ends. This enables, amongst others, the implementation of [[Communicating_sequential_processesCommunicating sequential processes|CSP]] based languages, languages based on the [[Pi calculus]]. The instruction set is agnostic as to where a channel is connected to - whether that is inside a core or outside the core. Channels carry messages constructed from data and control

tokens between the two channel ends. The control tokens can be

used to encode communication protocols.