Macrocell array: Difference between revisions

Revision as of 13:12, 15 September 2012

Revision as of 12:36, 20 January 2013

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{{Unreferenced|date=December 2009}}

{{Other uses|Macrocell (disambiguation)}}

A '''macrocell array''' is an approach to the design and manufacture of [[Application-specific integrated circuit|ASIC]]s. Essentially, it is a small step up from the otherwise similar [[gate array]], but rather than being a prefabricated array of simple logic gates, the macrocell array is a prefabricated array of higher-level logic functions such as [[Flip-flop (electronics)|flip-flop]]s, [[Arithmetic logic unit|ALU]] functions, [[Hardware register|register]]s, and the like. These logic functions are simply placed at regular predefined positions and manufactured on a [[wafer (electronics)|wafer]], usually called '''master slice'''. Creation of a circuit with a specified function is accomplished by adding metal interconnects to the chips on the master slice late in the manufacturing process, allowing the function of the chip to be customised as desired.