Princeton Application Repository for Shared-Memory Computers: Difference between revisions
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The '''Princeton Application Repository for Shared-Memory Computers''' (PARSEC) is a [[Benchmark (computing)|benchmark suite]] composed of multithreaded emerging workloads that is used to evaluate and develop next-generation [[multi-core processor|chip-multiprocessors]]. It was collaboratively created by [[Intel]] and [[Princeton University]] to drive research efforts on future computer systems.<ref name="ednnews">{{cite web
|title=Intel Teams with Universities on Multicore Software Suite
|url=http://www.edn.com/article/CA6364657.html
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}}</ref> For the first time in computer history software would have to be rewritten in order to take advantage of the parallel nature of those processors, which means that existing programs could not be used effectively to test and develop those new types of computer systems. At that time parallel software only existed in very specialized areas. However, before chip-multiprocessors became commonly available software developers were not willing to [[Parallelization|rewrite]] any mainstream programs, which means hardware manufacturers did not have access to any programs for test and development purposes that represented the expected real-world program behavior accurately. This posed a hen-and-egg problem that motivated a new type of benchmark suite with parallel programs that could take full advantage of chip-multiprocessors.
PARSEC was created to break this circular dependency. It was designed to fulfill the following five objectives:
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== Workloads ==
The PARSEC Benchmark Suite is available in version 2.1, which includes the following workloads:
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{{Reflist}}
▲===External links===
* [http://parsec.cs.princeton.edu/ The PARSEC Benchmark Suite]
* [http://wiki.cs.princeton.edu/index.php/PARSEC The PARSEC Wiki]
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