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{{Unreferenced stub|auto=yes|date=December 2009}}
An '''inter-processor interrupt''' ('''IPI''') is a special type of [[interrupt]] by which one processor may interrupt another processor in a [[multiprocessor]] system. IPIs are typically used to implement a [[cache coherency]] [[synchronization]] point.
== Mechanism ==
IPI signalling is often performed through the use of the [[Advanced Programmable Interrupt Controller|APIC]]. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which therefore issues a corresponding interrupt to its own CPU.
== Examples ==
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[[Category:Interrupts]]
== External Links ==
*[http://linux.linti.unlp.edu.ar/images/0/0c/ULK3-CAPITULO4-UNNOBA.pdf Interrupts and Exceptions]
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