XCore Architecture: Difference between revisions

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==Devices==
 
The XS1 instruction set is implemented by the [[XCore XS1-G4]], and[[XCore XS1-L1]], [[XCore XS1-L1SU]], and [[XCore XS1-AnA]]. The former is a four-core processing node, the latter athree are single and dual core processing nodenodes.
 
== References ==