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'''Synchronous Serial Interface (SSI)''' is a widely used serial interface standard for industrial applications between a master (e.g. controller) and a slave (e.g. sensor). SSI is based on [[
It was formerly covered by the German patent DE 34 45 617 which expired in 1990. It is very suitable for applications demanding reliability and robustness in measurements under varying industrial environments.
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In general, as mentioned earlier, it is a point to point connection from a master (e.g. PLC, Microcontroller) to a slave (e.g. [[Rotary_encoder|rotary encoders]]). The master controls the clock sequence and the slave transmits the current data/value through a shift register. When invoked by the master, the data is clocked out from the shift register. The master and slave are synchronized by the common clock of the controller.
The CLOCK and DATA signals are transmitted according to
Inputs can use an [[opto-coupler]] for galvanic isolation (For more details see [http://www.posital.sg/sg/products/POSITAL/AbsoluteEncoders_Context/AbsoluteEncoders_Context_Technology_SSI_AppNote.pdf]) that can be driven by RS-422/485 levels. The DATA output of the sensor is driven by a
== SSI
The interface has a very simple design as illustrated in the above figure. It consists of 2 pairs of wires, one for transmitting the clock signals from the master and the other for transmitting the data from the slave. The clock sequences are triggered by the master when need arises. Different clock frequencies can be used ranging from 100 kHz to 2 MHz and the number of clock pulses depends on the number of data bits to be transmitted.
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Readings from multiple slaves(up to 3) can be enabled at the same time by connecting them to a common clock. However, to avoid ground loops and electrically isolate the slave, complete galvanic isolation by opto-couplers is needed.
== SSI
The following keywords will be useful in understanding the SSI data transmission procedure.
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* LSB: Least significant bit
=== Single
[[Image:Ssisingletransmission.jpg|thumb|400px|right|Single Transmission of the SSI Interface: 1. Freezing of the data. 2. Transmission of the first Databit. 3. End of transmission. 4. after the pause time the SSI went back to idle state – is ready for new transmission.]]
The diagram illustrates the single data transmission using SSI protocol:
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The slave starts updating its value and the data line is set to HIGH (idle mode) if there are no clock pulses within time, tm. This marks the end of single transmission of the data word. Once the slave receives a clock signal at a time, tp (>=tm), the updated position value is frozen and the transmission of the value begins as described earlier.
=== Multiple
[[Image:Ssimultipletransmission.JPG|thumb|400px|right|Multiple transmission]]
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Multiple transmission is used to check the data integrity. The two consecutive received values are compared, transmission failures are indicated by differences between the two values.
=== Interrupting
The transmission of data is controlled by the master and the transmission can be interrupted at any time just by stopping the clock sequence, for a period longer than tm. The slave automatically will recognize the transfer timeout and go into idle mode.
==Cabling –
[[Image:Ssicablegraphrs.JPG|thumb|400px|right|Cable length versus signaling rate]]
Since SSI is based on
The relation between the cable length and clock frequency is shown in the following figure.<ref>[http://commtech-fastcom.com/SupportBlog/2010/05/06/rs422rs485-data-rate-cable-length/ *RS422 Cable Characteristics]</ref> This can be used as a conservative guide. This curve is based upon empirical data using a 24 [[American Wire Gauge|AWG]] Standard, copper conductor, unshielded [[Twisted-pair|twisted]]-pair telephone cable with a shunt capacitance of 52.5 pF/meter (16 pF/foot) terminated in a 100 Ohm resistive load. The cable length restriction shown by the curve is based upon assumed load signal quality requirements of:
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The type and length of the cable used must be capable of maintaining the necessary signal quality needed for the particular application. Furthermore, the cable balance must be such as to maintain acceptable crosstalk levels, both generated and received.
== Derived
Some manufacturers and organizations<ref>[http://www.biss-interface.com/ *Biss interface]</ref> added additional information to the basic SSI Protocol. It was done mainly to ensure proper data transmission. For secure transmission and to indicate the end of data transmission CRC bits or Parity bits can be added. In simple words, they were used for identifying if the byte has been correctly interpreted and received. In the original specification multiple transmissions were used to ensure data integrity. In this case, two consecutive transmissions of the same data were initiated and compared for any error in transmission. But this however reduces the protocol efficiency by 50% compared to parallel data transmission.
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* Serial data transfer has reduced the wiring. This, in addition to the simplicity of SSI design due to use of minimal number of components, has considerably reduced the cost and created more transmission bandwidth for message bits.
* High [[EM interference|Electromagnetic interference]] immunity due to
* Optimal [[galvanic isolation]]
* Complete protocol flexibility for the number of bits transferred. Not limited to a certain number of words and has an arbitrary choice of message size.
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