Synchronous Serial Interface: Difference between revisions

Revision as of 17:08, 24 July 2013

Revision as of 17:21, 24 July 2013

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After n-CLOCK pulses (rising edges) the data is completely transmitted. With the next CLOCK pulse (rising edge n+1) the sensor output goes to low level which can be used to detect a short circuit in the cable. If it is high even after n+1 rising edges then it means that the interface has a short circuit.

Readings from multiple slaves (up to 3three) can be enabled at the same time by connecting them to a common clock. However, to avoid ground loops and electrically isolate the slave, complete galvanic isolation by opto-couplers is needed.

== SSI timing and transmission ==

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The following keywords will be useful in understanding the SSI data transmission procedure.

* ‘tm’ represents the transfer timeout (Monoflopmonoflop time). It is the minimum time required by the slave to realise that the data transmission is complete. After tm, the data line goes to idle and the slave starts updating its data in the shift register.

* ‘tp’ represents the pause time. It is the time delay between two consecutive clock sequences from the master.

* ‘tw’ represents the repetition time. It is the minimum time elapsed between retransmissions of the same data and is always less than tm.

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The initial sequences are the same as that of the single transmission. In the idle state the CLOCK and DATA lines are high but with the arrival of the first falling edge the transmission mode is evoked and the similarly the data bits are transmitted sequentially starting with the MSB with every rising edge. The transmission of the LSB means that the transmission of the data is completed. An additional rising edge pushes the data line to LOW signifying the end of transmission of the particular data.

But, if there are continuous clock pulses even after then ( i.e. the next clock pulses comes in time tw (< tm )) the value of the slave is not updated. This is because the monoflop is still unsteady and the value in the shift register still contains the same value as before. So with the next rising edge, i.e. after the n+1 rising edge, the transmission of the same data continues and the MSB of data transmitted earlier is re-transmitted at the end of tw.

Then, it follows the same procedure as earlier transmissions, leading to multiple transmissions of the same data. The value of the slave is updated only when the timing between two clock pulses is more than the transfer timeout, tm.

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== Derived protocols ==

Some manufacturers and organizations<ref>[http://www.biss-interface.com/ *Biss interface]</ref> added additional information to the basic SSI Protocolprotocol. It was done mainly to ensure proper data transmission. For secure transmission and to indicate the end of data transmission CRC bits or Parityparity bits can be added. In simple words, they were used for identifying if the byte has been correctly interpreted and received. In the original specification multiple transmissions were used to ensure data integrity. In this case, two consecutive transmissions of the same data were initiated and compared for any error in transmission. But this however reduces the protocol efficiency by 50% compared to parallel data transmission.

== Benefits ==

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* Complete protocol flexibility for the number of bits transferred. Not limited to a certain number of words and has an arbitrary choice of message size.

* [[Master-slave (technology)|Slaves]] use master’s clock and hence don’t need precision oscillators.

* The SSI allows to connect up to 3three slaves to a common clock. Therefore, it is possible to attain values from multiple sensors.

The limitations in this interface are negligible for applications in industrial automation. SSI can handle only short distance communication ( up to 1.2&nbsp;km) and supports only one [[Master-slave (technology)|master]] device. But, 1.2&nbsp;km is rather a good distance for communication by automation industry standards. When compared to advanced communication systems based on field buses or Ethernet, SSI is limited to a master slave architecture and a simple point to point communication between a master and a [[Master-slave (technology)|slave]]. Another disadvantage is that there is no hardware [[Master-slave (technology)|slave]] acknowledgment i.e. detection of [[Master-slave (technology)|slave]] for communication.

== References ==