26-bit computing: Difference between revisions

Revision as of 13:51, 20 July 2012

Revision as of 21:29, 18 September 2013

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In the [[ARM Limited|ARM]] [[ARM_architecture|processor architecture]], '''26-bit''' refers to the design used in the original ARM processors, where the [[Program Counter]] ('''PC''') and [[Status_register|Processor Status Register]] ('''PSR''') were combined into one 32-bit [[Processor_registers|register]] (R15), the status flags filling the high 6 bits and the Program Counter taking up the lower 26 bits.

In fact, because the program counter is always word-aligned the lowest two bits are always zero which allowed the designers to reuse these two bits to hold the processor's mode bits too. The four modes allowed were USR26, SVC26, IRQ26, FIQ26; contrast this with the 32 possible modes available when the program status was separated from the program counter in more recent [[ARM Architecture|ARM architecturesarchitecture]]s.

This design enabled more efficient [[Computer_program|program]] execution, as the Program Counter and status flags could be saved and restored with a single operation. This resulted in faster [[subroutine]] calls and [[interrupt]] response than traditional designs, which would have to do two register loads or saves when calling or returning from a subroutine.

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==History==

Despite having a [[32-bit]] ALU and word-length, processors based on ARM Architecturearchitecture version 1 and 2 had only a 26-bit PC and [[address bus]], and were consequently limited to 64 MiB of addressable [[Random_Access_MemoryRandom Access Memory|memory]]. This was still a vast amount of memory at the time, but because of this limitation, architectures since have included various steps away from the original 26-bit design.

The ARM Architecturearchitecture version 3 introduced a 32-bit PC and separate PSR, as well as a 32-bit address bus, allowing 4 GiB of memory to be addressed. The change in the PC/PSR layout caused incompatibility with code written for previous architectures, so the processor also included a 26-bit compatibility mode which used the old PC/PSR combination. The processor could still address 4 GB in this mode, but could not [[Execution_(computers)|execute]] anything above address 3FFFFFC (64 MB). This mode was used by [[RISC OS]] running on the [[Risc_PC|Acorn Risc PC]] to utilise the new processors while retaining compatibility with existing software.

ARM Architecturearchitecture version 4 made the support of the 26-bit addressing modes optional, and ARM Architecturearchitecture version 5 onwards has removed them entirely.

==External links==