Glossary of reconfigurable computing: Difference between revisions

Revision as of 20:41, 24 March 2013

Revision as of 17:00, 20 October 2013

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{{defn|1=An Estrin architecture reconfigurable computer typically pairs a conventional microprocessor host computer with a reconfigurable co-processor, such as an [[FPGA]] or [[Reconfigurable Data Path Array|rDPA]] board. The co-processor can be reconfigured to perform different computations during execution of a host computer program by loading appropriate bitstreams. Newer FPGA-based architectures eliminate the need for a host processor by providing mechanisms to configure the device on boot from flash, and to directly support essential interfaces to memory and network resources via a bus configured in the device fabric.

Afairly recent market has developed for low-power reconfigurable system-on-chip ([[System-on-a-chip|SoC]]) devices that manufacturers can customize to their product applications, which are typically portable consumer media electronics. The devices typically incorporate one or more von NeumanNeumann processors, and provide mechanisms to extend the processor(s) instruction set and/or interface the device to other subsystems in the product. While these devices are technically "reconfigurable processors," they are really designed to be configured once during production, or to be reconfigured as part of a field upgrade, but not to be reconfigured on-the-fly.}}

{{term|1=Reconfigurable Computing}}

{{defn|1=A computing paradigm employing reconfigurable devices such as FPGAs or rDPAs to process data. A different bitstream can be loaded during the execution of a program or to run a different program on the fly. Estrin architecture reconfigurable computers include conventional von NeumanNeumann processors as main or control processors, and typically use one or more reconfigurable devices as co-processors. Newer FPGA-based architectures eliminate the need for a host processor by providing mechanisms to configure the device on boot from flash, and to directly support essential interfaces to memory and network resources via a bus configured in the device fabric. Providing a stable and stateful computational platform within a reconfigurable device requires, however, ''partial reconfigurability'' - that is, the ability to reconfigure only that portion of the device that implements an application, while leaving unchanged the portion of the device that implements the platform - the memory and network interfaces, the device drivers, and so forth. Current FPGA devices allow partial reconfiguration, but implementing designs that can effectively use this feature is still a tough exercise in system-on-chip design.}}

{{term|1=Reconfigurable Device}}