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Second, it is possible that a pattern(s) exist, but the algorithm cannot find it. Since the ATPG problem is [[NP-complete]] (by reduction from the [[Boolean satisfiability problem]]) there will be cases where patterns exist, but ATPG gives up since it will take an incredibly long time to find them (assuming [[P = NP problem|P≠NP]], of course).
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single fault assumption: only one fault occur in a circuit. if we define ''k'' possible fault types in our fault model the circuit has ''n'' signal lines, by single fault assumption, the total number of single faults is ''k×n''.
multiple fault assumption: multiple faults may occur in a circuit.
=== Fault collapsing ===
It is possible that Two or more faults, produce same faulty behavior for all input patterns. these faults are called equivalent faults. Any single fault from the set of equivalent faults can represent the whole set. In this case, much less than ''k×n'' fault tests are required for a circuit with ''n'' signal line. removing equivalent faults from entire set of faults is called fault collapsing.
==== The Stuck-at fault model ====
{{main|Stuck-at fault}}
In the past several decades, the most popular fault model used in practice is the single [[stuck-at fault]] model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. Hence, if a circuit has ''n'' signal lines, there are potentially ''2n'' stuck-at faults defined on the circuit, of which some can be viewed as being equivalent to others. The stuck-at fault model is a ''logical'' fault model because no delay information is associated with the fault definition. It is also called a ''permanent'' fault model because the faulty effect is assumed to be permanent, in contrast to ''intermittent'' faults which occur (seemingly) at random and ''transient'' faults which occur sporadically, perhaps depending on operating conditions (e.g. temperature, power supply voltage) or on the data values (high or low voltage states) on surrounding signal lines. The single stuck-at fault model is ''structural'' because it is defined based on a structural gate-level circuit model.
A pattern set with 100% stuck-at fault coverage consists of tests to detect every possible stuck-at fault in a circuit. 100% stuck-at fault coverage does not necessarily guarantee high quality, since faults of many other kinds—such as bridging faults, opens faults, and transition (aka delay) faults—often occur.
==== The transistor faults ====
This model is used to describe faults for CMOS logic gates. At transistor level, a transistor maybe stuck-short or stuck-open. In stuck-short, a transistor behaves as it is always conducts (or stuck-on), and stuck-open is when a transistor never conducts current (or stuck-off). Stuck-short will produce a short between VDD and VSS.
==== bridging faults ====
A short circuit between two signal lines is called bridging faults. bridging to VDD or Vss is equivalent to stuck at fault model. Traditionally both signals after bridging were modeled with logic AND or OR of both signals. If one driver dominates the other driver in a bridging situation, the dominant driver forces the logic to the other one, in such case a dominant bridging fault is used. To better reflect the reality of CMOS VLSI devices, a Dominant AND or Dominant OR bridging fault model is used. in the latter case, dominant driver keeps its value, while the other one gets the AND or OR value of its own and the dominant driver.
==== opens faults ====
==== Delay faults ====
== Combinational ATPG ==
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