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[[Image:Generic NCO.png|frame|Figure 1: Numerically controlled oscillator with optional quadrature output]]
When clocked, the phase accumulator (PA) creates a [[modulo operation|modulo]]-2<sup>N</sup> [[sawtooth wave]]form which is then converted by the phase-to-amplitude converter (PAC) to a sampled sinusoid, where N is the number of bits carried in the phase accumulator. N sets the NCO frequency resolution and is normally much larger than the number of bits defining the memory space of the PAC [[look-up table]]. If the PAC capacity is 2<sup>M</sup>, the PA output word must be truncated to M bits as shown in Figure 1. However, the truncated bits can be used for interpolation. The truncation of the phase output word does not affect the frequency accuracy but produces a time-varying periodic phase error which is a primary source of spurious products. Another spurious product generation mechanism is finite word length effects of the PAC output (amplitude) word.<ref name="kroupa">Kroupa,Venceslav F.,''Direct Digital Frequency Synthesizers'', IEEE Press, 1999, ISBN 0-7803-3438-8</ref>
The frequency accuracy relative to the clock frequency is limited only by the precision of the arithmetic used to compute the phase.<ref name="kroupa"/> NCOs are phase- and frequency-agile, and can be trivially modified to produce [[phase modulation|phase-modulated]] or [[frequency modulation|frequency-modulated]] by summation at the appropriate node, or provide [[quadrature phase|quadrature]] outputs as shown in the figure.
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<!-- linked from redirect [[Phase accumulator]] -->
A binary phase accumulator consists of an N-bit binary [[adder (electronics)|adder]] and a [[hardware register|register]] configured as shown in Figure 1.<ref name="Grzeg"/> Each clock cycle produces a new N-bit output consisting of the previous output obtained from the register summed with the frequency control word (FCW) which is constant for a given output frequency. The resulting output waveform is a staircase with step size <math>\Delta F</math>, the integer value of the FCW.<ref name="ADI"/> In some configurations, the phase output is taken from the output of the register which introduces a one clock cycle [[latency (engineering)|latency]] but allows the adder to operate at a higher clock rate.<ref name="latticeSC" />
[[Image:Phase Accum Graph.png|frame|Figure 2: Normalized phase accumulator output]]
The adder is designed to overflow when the sum of the [[absolute value]] of its operands exceeds its capacity (2<sup>N</sup>−1). The overflow bit is discarded so the output word width is always equal to its input word width. The remainder <math>\phi _n</math>, called the residual, is stored in the register and the cycle repeats, starting this time from <math>\phi _n</math> (see figure 2).<ref name="Grzeg"/> Since a phase accumulator is a [[finite state machine]], eventually the residual at some sample K must return to the initial value <math>\phi _0</math>. The interval K is referred to as the grand repetition rate (GRR) given by
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|contribution = Low-Spur Numerically Controlled Oscillator Using Taylor Series Approximation
|contribution-url = http://mechatronika.polsl.pl/owd/pdf2009/030.pdf
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|place = XI International PhD Workshop, Silesian University of Technology, Gliwice, Poland}}</ref> and methods which take advantage of the quadrature symmetry exhibited by sinusoids.<ref>{{Citation
|inventor-last =Mccallister
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