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== Mechanism ==
The [[OS/360 and successors#M65MP|M65MP]] option of [[OS/360 and successors|OS/360]] used the Direct Control feature of the [[IBM System/360|S/360]] to generate an interrupt on another processor; [[OS/360 and successors#OS/VS2 SVS and MVS|MVS]] uses the SIGNAL PROCESSOR instruction of the [[IBM System/370|S/370]], which provided a more formalized interface.
On [[IBM PC compatible]] computers that use the [[Advanced Programmable Interrupt Controller]] (APIC), IPI signalling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which therefore issues a corresponding interrupt to its own CPU.
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