Random testing: Difference between revisions

Revision as of 15:44, 19 October 2013

Revision as of 09:50, 8 January 2014

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== On randomness ==

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== Types of random testing ==

=== With respect to the input ===

* Random input sequence generation (i.e. a sequence of method calls)

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=== Guided vs. unguided ===

* undirected random test generation - with no heuristics to guide its search

* directed random test generation - f.ex. "feedback-directed random test generation"<ref name="PachecoLET2007">{{cite journal|last=Pacheco|first=Carlos|coauthors=Shuvendu K. Lahiri, Michael D. Ernst, Thomas Ball|title=Feedback-directed random test generation|journal=ICSE '07: Proceedings of the 29th International Conference on Software Engineering|year=2007|month=5May|pages=75-8475–84|url=http://people.csail.mit.edu/cpacheco/publications/feedback-random.pdf|publisher=IEEE Computer Society|issn=0270-5257}}</ref>

== Implementations ==

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== Critique ==

<blockquote>Random testing has only a specialized niche in practice, mostly because an effective oracle is seldom available, but also because of difficulties with the operational profile and with generation of pseudorandom input values.<ref name="Hamlet94"/></blockquote>

An Oracle is an instrument for verifying whether the outcomes match the program specification or not. An operation profile is knowledge about usage patterns of the program and thus which parts are more important.

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* [[Fuzz testing]] - a kind of random testing when invalid input is provided to tested program.

* [[Lazy systematic unit testing#Systematic Testing]] - a systematic way of exploring "all" method calls, as implemented e.g. by NASA's [http://babelfish.arc.nasa.gov/trac/jpf/wiki/intro/what_is_jpf Java Path Finder] (which blands [http://babelfish.arc.nasa.gov/trac/jpf/wiki/intro/testing_vs_model_checking testing with model checking] by limiting the state space to a reasonable size by various means)

* [[SystemVerilog#Constrained_random_generationConstrained random generation|Constrained random generation in SystemVerilog]]

== References ==