Automatic test pattern generation: Difference between revisions

Revision as of 15:10, 23 November 2013

Revision as of 07:52, 17 January 2014

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'''ATPG''' (acronym for both '''A'''utomatic '''T'''est '''P'''attern '''G'''eneration and '''A'''utomatic '''T'''est '''P'''attern '''G'''enerator) is an [[electronic design automation]] method/technology used to find an input (or test) sequence that, when applied to a [[digital circuit]], enables [[automatic test equipment]] to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The generated patterns are used to test semiconductor devices after manufacture, and in some cases to assist with determining the cause of failure ([[failure analysis]].<ref>{{cite conference| last=Crowell| first=G| coauthorsauthor2=Press, R.| title=Using Scan Based Techniques for Fault Isolation in Logic Devices| booktitle=Microelectronics Failure Analysis | pages= 132–8}}</ref>) The effectiveness of ATPG is measured by the amount of modeled defects, or [[fault models]], that are detected and the number of generated patterns. These metrics generally indicate [[test quality]] (higher with more fault detections) and test application time (higher with more patterns). ATPG efficiency is another important consideration. It is influenced by the fault model under consideration, the type of circuit under test ([[Scan chain|full scan]], synchronous sequential, or asynchronous sequential), the level of abstraction used to represent the circuit under test (gate, register-transistor, switch), and the required [[Fault coverage|test quality]].

== Basics of ATPG ==

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=== Fault collapsing ===

It is possible that Two or more faults, produce same faulty behavior for all input patterns. these faults are called equivalent faults. Any single fault from the set of equivalent faults can represent the whole set. In this case, much less than ''k×n'' fault tests are required for a circuit with ''n'' signal line. removing equivalent faults from entire set of faults is called fault collapsing.

==== The Stuck-at fault model ====

{{main|Stuck-at fault}}

In the past several decades, the most popular fault model used in practice is the single [[stuck-at fault]] model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. Hence, if a circuit has ''n'' signal lines, there are potentially ''2n'' stuck-at faults defined on the circuit, of which some can be viewed as being equivalent to others. The stuck-at fault model is a ''logical'' fault model because no delay information is associated with the fault definition. It is also called a ''permanent'' fault model because the faulty effect is assumed to be permanent, in contrast to ''intermittent'' faults which occur (seemingly) at random and ''transient'' faults which occur sporadically, perhaps depending on operating conditions (e.g. temperature, power supply voltage) or on the data values (high or low voltage states) on surrounding signal lines. The single stuck-at fault model is ''structural'' because it is defined based on a structural gate-level circuit model.

A pattern set with 100% stuck-at fault coverage consists of tests to detect every possible stuck-at fault in a circuit. 100% stuck-at fault coverage does not necessarily guarantee high quality, since faults of many other kinds—such as bridging faults, opens faults, and transition (aka delay) faults—often occur.

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Sequential-circuit ATPG searches for a sequence of vectors to detect a particular fault through the [[State space|space of all possible vector sequences]]. Various search strategies and heuristics have been devised to find a shorter sequence and/or to find a sequence faster. However, according to reported results, no single strategy/heuristic out-performs others for all applications/circuits. This observation implies that a test generator should include a comprehensive set of heuristics.

Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit. Also, due to the presence of memory elements, the [[controllability]] and [[observability]] of the internal signals in a [[sequential circuit]] are in general much more difficult than those in a [[combinational logic]] circuit. These factors make the complexity of sequential ATPG much higher than that of combinational ATPG, where a scan-chain (i.e. switchable, for-test-only signal chain) is added to allow simple access to the individual nodes.

Due to the high complexity of the sequential ATPG, it remains a challenging task for large, highly sequential circuits that do not incorporate any [[Design For Test]]ability (DFT) scheme. However, these test generators, combined with low-overhead DFT techniques such as [[partial scan]], have shown a certain degree of success in testing large designs. For designs that are sensitive to area and/or performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG.