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That cat seems to contain only processors, not any related chips. removed Category:PowerPC implementations using HotCat |
I think all of them |
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IBM however developed their '''MultiProcessor Interrupt Controller''' ('''MPIC''') based on the OpenPIC register specification.<ref name="mpic db"/> In the reference IBM design, the processors share the MPIC over a [[CoreConnect|DCR bus]], with their access to the bus controlled by a DCR Arbiter. MPIC supports up to four processors and up to 128 interrupt sources.<ref name="mpic db">IBM [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf Multiprocessor Interrupt Controller. Data Book]</ref>
Through various implementations, the MPIC was included used in some [[PowerPC]] reference designs and concrete computers. IBM used a MPIC based on OpenPIC 1.0 in their [[RS/6000]] F50 and one based on OpenPIC 1.2 in their RS/6000 S70. Both of these systems used a dual [[8259]] on their PCI-ISA bridges.<ref>Arca Systems TTAP Evaluation Facility [http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security], p. 29</ref> An IBM MPIC was also used in the RS/6000 7046 Model B50.<ref>RS/6000 7046 Model B50 Handbook, November 1999, IBM document G24-7046-00, p. 107</ref> The [[Apple Inc.|Apple]] Hydra chip (from the 1990s [[MacOS]] era) implemented a MPIC alongside a [[SCSI]] controller, [[Apple Desktop Bus|ADB]] controller, [[GeoPort]] controller, and timers.<ref>[http://cache.freescale.com/files/archives/doc/ref_manual/YKNIFEX4HW.pdf Yellowknife Reference Platform Hardware Design Manual], p. 11</ref> The MPIC was also incorporated in the newer K2 I/O controller used in
== See also ==
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