OpenPIC and MPIC: Difference between revisions

Revision as of 13:49, 12 February 2014

Revision as of 13:50, 12 February 2014

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Through various implementations, the MPIC was included used in some [[PowerPC]] reference designs and concrete computers. IBM used a MPIC based on OpenPIC 1.0 in their [[RS/6000]] F50 and one based on OpenPIC 1.2 in their RS/6000 S70. Both of these systems used a dual [[8259]] on their PCI-ISA bridges.<ref>Arca Systems TTAP Evaluation Facility [http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security], p. 29</ref> An IBM MPIC was also used in the RS/6000 7046 Model B50.<ref>RS/6000 7046 Model B50 Handbook, November 1999, IBM document G24-7046-00, p. 107</ref> The [[Apple Inc.|Apple]] Hydra [[Mac I/O]] (MIO) chip (from the 1990s [[MacOS]] era) implemented a MPIC alongside a [[SCSI]] controller, [[Apple Desktop Bus|ADB]] controller, [[GeoPort]] controller, and timers.<ref>[http://cache.freescale.com/files/archives/doc/ref_manual/YKNIFEX4HW.pdf Yellowknife Reference Platform Hardware Design Manual], p. 11</ref> The Apple implementation of "Open PIC" (as the Apple documentation of this era spells it) in their first MIO chip for the [[Common Hardware Reference Platform]] was based on version 1.2 of the register specification and supported up to two processors and up to 20 interrupt sources.<ref>Macintosh Technology in the Common Hardware Reference Platform, section "2.4.7 Open PIC Interrupt Controller", p. 11, ISBN 155860393X</ref> The MPIC was also incorporated in the newer K2 I/O controller used in the [[Power Mac G5]]s.<ref>[http://www.informit.com/articles/article.aspx?p=606582 Take a Look Inside the G5-Based Dual-Processor Power Mac]</ref><ref>[https://developer.apple.com/legacy/library/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/PowerMacG5.pdf Power Mac G5 Developer Note (Legacy)], p. 26</ref>

[[Freescale]] also uses a MPIC ("compatible with the Open PIC") on all its [[PowerQUICC]] and [[QorIQ]] processors.<ref>[https://www.kernel.org/doc/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt Freescale MPIC Interrupt Controller Node]</reF> The Linux [[Kernel-based Virtual Machine]] (KVM) supports a virtualized MPIC with up to 255256 interrupts, based on the Freescale variants.<ref>https://github.com/torvalds/linux/blob/master/Documentation/virtual/kvm/devices/mpic.txt</ref>

== See also ==