Power Processing Element: Difference between revisions

Revision as of 19:25, 11 February 2014

Revision as of 21:34, 26 February 2014

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| l2cache =

| l3cache =

| gpu = [[Xenos (graphics chip)|Xenos]], in the [[Xenon_Xenon (processor)#XCGPU|XCGPU]] variant.

| application = [[Video game console|Gaming Console]], [[High Performance Computing|HPC]]

| predecessor =

| successor =

| variant = [[Cell (microprocessor)|Cell BE]], [[Xenon (processor)|XCPU]], [[Xenon_Xenon (processor)#XCGPU|XCGPU]], [[Cell processor#PowerXCell 8i|PowerXCell 8i]]

}}

The '''Power Processing Unit''' (PPU) is a [[64-bit]] [[Multithreading (computer architecture)|dual threaded]] [[Out-of-order execution|in-order]] [[Power Architecture]] [[microprocessor]] [[Multi-core processor|core]] designed by [[IBM]] for use primarily in the [[game console]]s [[Playstation 3]] and [[Xbox 360]], but has also found applications in high performance computing in [[supercomputer]]s such as the record setting [[IBM Roadrunner]].

In most instances the PPU is joined by a 512 KB L2to form what is called the Power Processing Elemtn (PPE).

The PPU is used as a main CPU core in three different processor designs:

* The [[Cell (microprocessor)|Cell Broadband Engine]] (Cell BE) which is used primarily in [[Sony]]'s [[Playstation 3]] gaming console. It uses the PPE and comes in three versions, a 90  nm, a 65  nm and a 45  nm part.

* The [[Cell (microprocessor)#PowerXCell 8i|PowerXCell 8i]] which is a version of the Cell BE with enhanced FPU and memory subsystem. It was only manufactured as a singe 65  nm version.

* The [[Xenon_Xenon (processor)|XCPU]] which is used in a three core configuration and a unified 1 MB L2 cache inside Microsoft's [[Xbox 360]]. It comes in three versions, the 90  nm and 65  nm versions, and the 45  nm [[Xenon_Xenon (processor)#XCGPU|XCGPU]] with an integrated [[Graphics processing unit|graphics processor]] from [[ATI]].

== Main features ==

* 64-bit, dual-threaded core

* Typical 3.2  GHz clockrate

* 32 KB [[CPU cache|L1 Instruction cache]]

* 32 KB [[CPU cache|L1 Data cache]]

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== Floating Point Capacity ==

Its [[64-bit]] [[Single-precision floating-point format|single precision]] floating-point unit, and [[128-bit]] VMX unit (using the [[AltiVec]] instruction set), can perform a theoretical 12 floating-point operations per cycle, as all Power Architecture floating-point units can do floating-point mulitplymultiply-adds, and come no smaller than 64-bits. That gives 3.2 billion clock cycles * 12 = 38.4 billion floating-point operations/second.

The PPU is enhanced in the [[Cell processor#PowerXCell 8i|PowerXCell 8i]] processor to be able to make single cycle [[Double-precision floating-point format|double precision floating point]] operations, tailored for high performance computing in supercomputers.