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A straightforward approach to this issue may be to emulate the circuit on a [[field-programmable gate array]] instead. [[Formal verification]] can also be explored as an alternative to simulation, although a formal proof is not always possible.
A prospective way to accelerate logic simulation is using [[distributed computing|distributed]] and [[parallel computing|parallel]] computations.
To help gauge the thoroughness of a simulation, tools exist for assessing [[code coverage]], functional coverage and logic coverage tools.
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In cycle simulation, it is not possible to specify delays. A cycle-accurate model is used, and every gate is evaluated in every cycle. Cycle simulation therefore runs at a constant speed, regardless of activity in the model. Optimized implementations may take advantage of low model activity to speed up simulation by skipping evaluation of gates whose inputs didn't change. In comparison to event simulation, cycle simulation tends to be faster, to scale better, and to be better suited for hardware acceleration / emulation.
However, chip design trends point to event simulation gaining relative performance due to activity factor reduction in the circuit (due to techniques such as [[clock gating]] and [[power gating]], which are becoming much more commonly used in an effort to reduce power dissipation). In these cases, since event simulation only simulates necessary events, performance may no longer be a disadvantage over cycle simulation. Event simulation also has the advantage of greater flexibility, handling design features difficult to handle with cycle simulation, such as [[asynchronous logic]] and incommensurate clocks. Due to these considerations, almost all commercial logic simulators have an event based capability, even if they primarily rely on cycle based techniques.
== See also==
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