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The SCCC decoder includes two soft-in-soft-out (SISO) decoders and an interleaver. While shown as separate units, the two SISO decoders may share all or part of their circuitry. The SISO decoding may be done is serial or parallel fashion, or some combination thereof. The SISO decoding is typically done using [[Maximum a posteriori]] (MAP) decoders using the [[BCJR]] algorithm.
== LDPC Encoder ==
Figure X provides an illustration of the functional components of most LDPC encoders.
[[File:LDPC encoder Figure.png|thumb|none|500px|Fig. 1. LDPC Encoder]]
During the encoding of a frame, the input data bits (D) are repeated and distributed to a set of constituent encoders. The constituent encoders are typically accumulators and each accumulator is used to generate a parity symbol. A single copy of the original data D is transmitted (S) with the parity bits (P) to make up the code symbols. The S bits from each constituent encoder are discarded.
In some cases a parity bit is encoded by a second constituent code (serial concatenation), but more typically the constituent encoding for the LDPC is done in parallel.
In an example using the DVB-S2 rate 2/3 code the encoded block size is 64800 symbols (N=64800) with 42300 data bits (K=43200) and 21600 parity bits ( M=21600). Each constituent code (check node) encodes 16 data bits except for the first party bit which encodes 8 data bits. The first 4680 data bits are repeated 13 times (used in 13 parity codes), while the remaining data bits are used in 3 parity codes (irregular LDPC code).
For comparison, classic turbo codes typically use two convolutional codes of moderate depth (8 or 16 state) configured in parallel, each of which encodes the entire input block (K) of data bits. These constituent encoders are combined with a code interleaver which interleaves one copy of the frame to generate the parity symbols.
The LDPC, in contrast, uses many low depth (2 state) 'convolutional codes' (accumulators) in parallel, each of which encode only a small portion of the input frame. The many constituent codes are connected via the repeat and distribute operations which perform the function of the interleaver in the turbo code.
The ability to more precisely manage the connections of the various constituent codes and the level of redundancy for each input bit give more flexibility in the design of LDPC codes, which can lead to slightly better performance than turbo codes in some instances. Turbo codes still seem to perform better than LDPCs at low code rates, or at least the design of good performing low rate codes is easier for Turbo Codes.
As a practical matter, the hardware that forms the accumulators is reused during the encoding process. That is, once a first set of party bits are generated and the parity bits stored, the same accumulator hardware is used to generate a next set of parity bits.
== Performance ==
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