Revision as of 16:20, 21 May 2014 edit Comp.arch (talk \| contribs) Extended confirmed users 41,494 edits Six operands how? Double length instructions? Not all single cycle. "including a divide and remainder (which are the only instructions that are not single cycle)" - https://www.xcore.com/forum/viewtopic.php?f=7&t=873 ← Previous edit		Revision as of 01:17, 1 July 2014 edit undo Chris the speller (talk \| contribs) Autopatrolled, Extended confirmed users, Pending changes reviewers 894,195 edits m →Instruction encoding: per WP:HYPHEN, sub-subsection 3, points 3,4,5, replaced: rarely- → rarely using AWB Next edit →
Line 97: One 10-bit immediate opcode (PFIX, opcode 111100) is used to add an additional 10 bits to the 6- or 10-bit immediate in the following instruction. One 3-operand opcode (EOPR, opcode 11111) is reserved for an "additional operands" prefix. Its 3 operands are used along with those of the following instruction word to produce additional 32-bit instructions with up to 6 operands. This is also used for rarely- used 3- and 2-operand instructions; in such cases the EOPR specifies all 3 or 2 operands, and the following instruction word is a 0-operand instruction. (In the 2-operand case, the extra opcode bit in the leading EOPR ''is'' used.) ==Sequential programming model==

XCore Architecture: Difference between revisions