XCore Architecture: Difference between revisions

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m Instruction encoding: per WP:HYPHEN, sub-subsection 3, points 3,4,5, replaced: rarely- → rarely using AWB
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==Architecture==
The architecture comprises a central execution unit that operates on a set of 25 registers, aand surrounded by a number of ''resources'' that perform operations that interact with the environment. Each thread has its own set of hardware registers, enabling threads to execute concurrently.
The instruction set comprises both a (more or less standard) sequential programming model, and instructions that implement multi-threading, multi-core and I/O operations.