Design for testing: Difference between revisions

Revision as of 13:26, 2 June 2006

Revision as of 19:07, 4 July 2006

Line 31:

== Scan design ==

The most common method for delivering test data from chip inputs to internal ''circuits under test'' (CUTs, for short), and observing their outputs, is called scan-design. In scan-design, registers ([[Flip-flop (electronics)|flip-flop]]s or [[latchLatch (electronic)|latches]]es) in the design are connected in one or more [[scan chain]]s, which are used to gain access to internal nodes of the chip. Test patterns are shifted in via the scan chain(s), functional [[clock signal]]s are pulsed to test the circuit during the "capture cycle(s)", and the results are then shifted out to chip output pins and compared against the expected "good machine" results.

== Debug using DFT features ==