Data structure alignment: Difference between revisions

Revision as of 16:51, 28 June 2006

Revision as of 14:31, 6 July 2006

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* Writes not aligned to the width of the memory bus require two reads and two writes.

* Accesses across [[cache-lines]] require evicting two cache-lines.

* Accesses across page boundaries can incur two [[translation lookaside buffer|TLB]] misses and could even require swapingswapping in both pages from disk

==Compatibility==