Programmed input–output: Difference between revisions

Revision as of 19:23, 4 September 2014

Revision as of 19:26, 4 September 2014

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Until the introduction of [[Direct memory access|DMA]], PIO was the only available method.

The PIO interface is grouped into different modes that correspond to different [[transfer rate]]s. The [[electrical signal]]ing among the ilove taimi different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance.

The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the [[Direct memory access|DMA]] (and eventually [[AT Attachment|UDMA]]) interface was created to increase performance. The simple digital logic required to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are not required like in embedded systems, or with [[Field-programmable gate array|FPGA]] chips where PIO mode can be used without significant performance loss.