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→top: Described the Intel's lockstep memory layout (SDDC and DDDC), will add references in a few minutes |
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To run in lockstep, each system is set up to progress from one well-defined state to the next well-defined state. When a new set of inputs reaches the system, it processes them, generates new outputs and updates its state. This set of changes (new inputs, new outputs, new state) is considered to define that step, and must be treated as an atomic transaction; in other words, either all of it happens, or none of it happens, but not something in between. Sometimes a timeshift (delay) is set between systems, which increases the detection probability of errors induced by external influences (e.g. [[voltage spike]]s, [[ionizing radiation]], or [[in situ]] [[reverse engineering]]).
Some vendors, including Intel, use the term ''lockstep memory'' to describe a [[Multi-channel memory architecture|multi-channel]] memory layout in which [[cache line]]s are distributed between two memory channels, so one half of the cache line is stored in a [[DIMM]] on the first channel, while the second half goes to a DIMM on the second channel. By combining the [[single error correction and double error detection]] (SECDED) capabilities of two [[ECC memory|ECC]]-enabled DIMMs, in a lockstep layout their ''single-device data correction'' (SDDC) nature can be extended into ''double-device data correction'' (DDDC), thus providing protection against the failure of any single memory chip. Downsides of the Intel's lockstep memory layout are the reduction of effectively usable amount of RAM (in case of a triple-channel memory layout, maximum amount of memory reduces to one third of the physically available maximum), and reduced performance of the memory subsystem.
==Dual Modular Redundancy==
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