Deep reactive-ion etching: Difference between revisions

Revision as of 18:17, 10 June 2006

Revision as of 20:18, 10 July 2006

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RIE "deepness" depends on application: in DRAM memory circuits capacitor trenches may be 10-20 micrometers deep, while in MEMS DRIE is used for anything from a few micrometers to 0.5 mm. What distinguishes DRIE from RIE is actually etch rate: while 1 micrometre/minute is reasonable etch rate for RIE (as used in IC manufacturing), DRIE rates are 5-10 micrometres per minute.

There are two main technologies for high rate DRIE: cryogenic and Bosch (a.k.a.also known as time multiplexed or pulsed etching). In cryo-DRIE the wafer is cooled down to -110 degrees Celsius, which slows down spontaneous chemical (isotropic) etching, and only the ion bombardment driven etching of horizontal surfaces proceeds. Another mechanism is sidewall passivation: SiOxFy moieties (which originate from sulphur hexafluoride and oxygen etch gases) condensate on the sidewalls, and protect them from lateral etching. As a combination of these processes deep vertical structures can be made.

In the Bosch process there are three primary steps which are brought together to achieve nearly vertical structures. First a highly reactive gas (SF6) is used to perform a nearly [[isotropic]] etch of the [[substrate]]. After a brief period (say 5-15 seconds) the etching is stopped and the process switches over to deposition: C4F8 source gas is used to deposit a Teflon-like passivation layer over the whole surface (this takes a few seconds). This polymer layer protects the substrate from further chemical attack and prevents further etching. The process now returns to etching with SF6, which is where the third process comes into play. Within the chamber there is an energetic [[Plasma (physics)|plasma]] which produces a [[collimated]] stream of [[ion]]s that bombard the substrate. By a process of [[sputtering]] these ions remove the passivation layer from the bottom of the previously etched trench, but not from the sides. Etching therefore is preferentially in the vertical direction. These etch/deposit steps are repeated many times over resulting in a large number of very small [[isotropic]] etch steps taking place only at the bottom of the etched pits. To etch through a 0.5 mm silicon wafer, for example 100-1000 etch/deposit steps are needed. A closer look at Bosch process etched sidewall shows undulation which has an amplitude of ca. 100-500 nm depending on whether the process was optimized for high rate or vertical walls or sidewall smoothness. Cryo etched sidewalls are smooth. In both Bosch and cryo processes 90 degrees truly vertical walls can be fabricated but often the walls are slightly tapered, e.g. 88 or 92 degrees (which is said to be retrograde).