Logic simulation: Difference between revisions

Revision as of 22:22, 16 May 2014

Revision as of 06:16, 8 November 2014

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* [[Logic synthesis]]

* [[Logisim]]

* [[Digital-Logic-Design]]<ref>http://sourceforge.net/projects/digitalcircuitdesign/?source=directory</ref>

* [[List of Verilog simulators]]

* [[Functional verification]]