A Block diagram Language: Difference between revisions

Revision as of 20:07, 3 September 2014

Revision as of 11:33, 6 January 2015

Line 1:

{{Multiple issues|notability =August 2008|COI =July 2009|unreferencd = August 2014}}|

{{notability|date=August 2008}}

{{COI|date=July 2009}}

}}

'''A Block diagram Language (ABL)''' is the graphic companion language of the textual [[hardware description language]] KARL (the KAiserslautern Register Transfer Language, a language at the [[register transfer level]]), which supports [[Structured hardware design]]. It has been authored by [[Reiner Hartenstein]] and jointly implemented by the [[Xputer]] Lab at [[TU Kaiserslautern]] and Guglielmo Girardi at [[CSELT]], Torino, Italy, as the ABLED interactive graphic hardware design editor with automatic interconnect compatibility check. The [[Domino notation]] of ABL is based on structured wiring function primitives and topological notations of [[KARL]] and allows interactive interconnect synthesis by module block abutment. A couple of other design tools are based on these calculus-like notations, like ARIANNA (interactive chip floor plan generator, and GENMON from [[CSELT]]), the BACH compiler, an [[ASIC]] Data path module generator, and others.