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== {{Anchor|MEMORY}}Lockstep memory ==
Some vendors, including Intel, use the term ''lockstep memory'' to describe a [[Multi-channel memory architecture|multi-channel]] memory layout in which [[cache line]]s are distributed between two memory channels, so one half of the cache line is stored in a [[DIMM]] on the first channel, while the second half goes to a DIMM on the second channel. By combining the [[single error correction and double error detection]] (SECDED) capabilities of two [[ECC memory|ECC]]-enabled DIMMs in a lockstep layout, their ''single-device data correction'' (SDDC) nature can be extended into ''double-device data correction'' (DDDC), providing protection against the failure of any single memory chip.<ref name="intel-xeon-e7-v2">{{cite web
| url = https://software.intel.com/en-us/articles/intel-xeon-processor-e7-v2-family-technical-overview#c104
| title = Intel Xeon Processor E7 V2 Family Technical Overview, Section 3.1: Intel C104/102 Scalable Memory Buffer
| date = 2014-02-18 | accessdate = 2014-09-09
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| author = Thomas Willhalm | publisher = [[Intel]]
}}</ref><ref name="hp-proliant-guidelines">{{cite web
| url = ftp://ftp.hp.com/pub/c-products/servers/options/Memory-Config-Recommendations-for-Intel-Xeon-5500-Series-Servers-Rev1.pdf#page=8
| title = Best Practice Guidelines for ProLiant Servers with the Intel Xeon 5500 processor series Engineering Whitepaper, 1st Edition
| date = May 2009 | accessdate = 2014-09-09
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}}</ref>
Downsides of the Intel's lockstep memory layout are the reduction of effectively usable amount of RAM (in case of a triple-channel memory layout, maximum amount of memory reduces to one third of the physically available maximum), and reduced performance of the memory subsystem.<ref name="intel-xeon-e7-v2
== Dual modular redundancy ==
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