Revision as of 09:05, 25 January 2015 edit Dsimic (talk \| contribs) Extended confirmed users, Pending changes reviewers, Rollbackers 39,664 edits →Lockstep memory: Reference improvemens; Second parapgraph needs only two references ← Previous edit		Revision as of 09:18, 25 January 2015 edit undo Dsimic (talk \| contribs) Extended confirmed users, Pending changes reviewers, Rollbackers 39,664 edits →Lockstep memory: Added a reference Next edit →
Line 27: \| title = Best Practice Guidelines for ProLiant Servers with the Intel Xeon 5500 processor series Engineering Whitepaper, 1st Edition \| date = May 2009 \| accessdate = 2014-09-09 \| publisher = [[HP]] \| format = PDF ~~\| format = PDF~~ \| pages = 8–9 }}</ref><ref>{{cite web \| url = http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/c102-c104-scalable-memory-buffer-datasheet.pdf#page=9 \| title = Intel C102/C104 Scalable Memory Buffer Datasheet, Section 1.3.1.2.2: 1:1 Sub-channel Lockstep Mode \| date = February 2014 \| accessdate = 2015-01-25 \| publisher = [[Intel]] \| format = PDF \| page = 9 }}</ref>

Lockstep (computing): Difference between revisions