Single instruction, multiple threads: Difference between revisions

Revision as of 23:57, 29 January 2015

Revision as of 23:58, 29 January 2015

Line 1:

'''Single instruction, multiple thread''' (SIMT) is an [[parallel computing|parallel]] execution model, used in some [[GPGPU]] platforms, where dynamic multithreading is simulated by [[SIMD]] processors. The processors, say a number {{mvar|p}} of them, seem to be executed many more than {{mvar|p}} tasks. The threads (or tasks) are in fact partitioned into blocks that map onto the processors, and these blocks execute tasks in lock-step.<ref name="spp">{{cite book |author1=Michael McCool |author2=James Reinders |author3=Arch Robison |title=Structured Parallel Programming: Patterns for Efficient Computation |publisher=Elsevier |year=2013 |pagespage=209 ff.52}}</ref>

SIMT introduced by [[Nvidia]]:<ref>{{cite web |url=http://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf |title=Nvidia Fermi Compute Arcitecture Whitepaper |date=2009 |website=http://www.nvidia.com/ |publisher=NVIDIA Corporation |accessdate=2014-07-17}}</ref><ref name=teslaPaper>{{cite web |url=http://dx.doi.org/10.1109/MM.2008.31 |title=NVIDIA Tesla: A Unified Graphics and Computing Architecture |date=2008 |website=http://www.ieee.org/ |publisher=IEEE |accessdate=2014-08-07 |page=6 {{subscription required|s}} }}</ref>