Content deleted Content added
→See also: Will link it in a section |
→Lockstep memory: Added a {{See also}} link |
||
Line 13:
== {{Anchor|MEMORY}}Lockstep memory ==
{{See also|Chipkill}}
Some vendors, including Intel, use the term ''lockstep memory'' to describe a [[Multi-channel memory architecture|multi-channel]] memory layout in which [[cache line]]s are distributed between two memory channels, so one half of the cache line is stored in a [[DIMM]] on the first channel, while the second half goes to a DIMM on the second channel. By combining the [[single error correction and double error detection]] (SECDED) capabilities of two [[ECC memory|ECC]]-enabled DIMMs in a lockstep layout, their ''single-device data correction'' (SDDC) nature can be extended into ''double-device data correction'' (DDDC), providing protection against the failure of any single memory chip.<ref name="intel-xeon-e7-v2">{{cite web
| url = https://software.intel.com/en-us/articles/intel-xeon-processor-e7-v2-family-technical-overview#c104
| |||