Pass transistor logic: Difference between revisions

Revision as of 18:13, 5 March 2015

Revision as of 13:53, 30 March 2015

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CPL uses series transistors to select between possible inverted output values of the logic, the output of which drives an [[Inverter (logic gate)|inverter]] The CMOS transmission gates consist of nMOS and pMOS transistor connected in parallel.

==Double pass transistor logic==

Double-pass transistor logic eliminates some of the inverter stages required for complementary pass transistor logic by using both N and P channel transistors, with dual logic paths for every function. While it has high speed due to low input capacitance, it has only limited capacity to drive a load.

==Other forms==