Bus encoding: Difference between revisions

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# '''Sequential addressing or T0 codes'''<ref>L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, “Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems,” Proc. Seventh Great Lakes Symposium on VLSI, pp. 77-82, Mar.1997.</ref>: In case of address bus, due to spatial locality that exists in programs, most of the transitions involve changing the address to the next consecutive value. A possible encoding scheme is to use an additional line, INC, in the bus indicating whether the current transition is the next increment address or not. If it is not a consecutive address, then the receiver can use the value on the bus. But if it is a consecutive address, the transmitter need not change the value in the bus, but just assert the INC line to 1. In such case, for a continuous addressing scheme, there is no transition at all on the bus, leading to a bus activity factor of 0.

# '''Number representation''': Let us consider an example of a system which gets one of its data from a sensor. Most of the times, the sensor may be measuring some noise and for this example, let us consider that the values being measured are (0) and (-1) alternatively. For a 32-bit data bus, value 0 translates to 0x00000000 (0000 0000 0000 0000 0000 0000 0000 0000) while (-1) translates to 0xFFFFFFFF (1111 1111 1111 1111 1111 1111 1111 1111) in a 2’s complement representation. We see that the hamming distance in this case is 32 (since all 32-bits are changing their state). Instead, if we encode the bus to use signed integer representation (MSB is sign bit), we can represent 0 as 0x00000000 (0000 0000 0000 0000 0000 0000 0000 0000) and -1 as 0x80000001 (1000 0000 0000 0000 0000 0000 0000 0001) . In this case, we see that the hamming distance between the numbers is just 2. Hence by using a 2’s complement to signed arithmetic encoding, we are able to reduce the activity from a factor of 32 to 2.

# '''Inversion Coding'''<ref>M. R. Stan and W. P. Burleson, “Bus-invert coding for low-power I/O,” IEEE Transactions On VLSI Systems, Vol.3, No.1, pp.49-58, 1995</ref><ref>http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Fall07/PROJECT/JIANG/Low%20power%2032-bit%20bus%20with%20inversion%20encoding.ppt</ref>: This is another implementation of bus encoding where an additional line named INV is added to the bus lines. Depending on the value of the INV line, the other lines will be used with or without inversion. e.g. if INV line is 0, the data on the bus is sampled as it is but if INV line is 1, the data on the bus is inverted before any processing on it. ReferingReferring to the example used in 3, instead of using a signed integer representation, we could continue using 2’s complement and achieve the same activity reduction using inversion encoding. 0 will be represented as 0x00000000 with INV=0. -1 will be represented as 0x00000000 with INV=1. Since INV=1, receiver will invert the data before consuming it, thereby converting it to 0xFFFFFFFF internally. In this case, only 1 bit (INV bit) is changed over bus leading to an activity of factor 1. In general, in inversion encoding, the encoder computes the hamming distance between the current value and next value and based on that, determines whether to use INV=0 or INV=1.

#'''Other techniques''' like Sector Based Encoding<ref>http://sportlab.usc.edu/~massoud/Papers/sector-based-encoding-journal.pdf</ref>, variations of Inversion coding, have also been proposed. There has been work on using bus encodings which lower the leakage power consumption as well along with reducing the crosstalk with minimal impact on path delays.<ref>H. Deogun, R. R. Rao, D. Sylvester, and D. Blaauw. Leakage-and crosstalk-aware bus encoding for total power reduction. In Proceedings of the 41st Design Automation Conference, pages 779–782, June 2004.</ref><ref>Z. Khan, T. Arslan, and A. Erdogan. A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systems. In Proceedings of the 18th International Conference on VLSI Design , pages 751–756. IEEE Computer Society, January 2005.</ref>