Revision as of 12:11, 27 July 2015 edit Imzadi (talk \| contribs) 6 edits m →Bridging faults: typo ← Previous edit		Revision as of 00:10, 9 November 2015 edit undo 72.208.196.188 (talk) →Delay faults: fixed typo Next edit →
Line 35: * Gate delay fault * Transition fault * Path delay fault: This fault is due to the sum of all gate propagation delays along a single path. This fault shows that the delay of one or more paths exceeds the clock period. ~~one~~One major problem in finding delay faults is the number of possible paths in a circuit under test (CUT), which in the worst case can grow exponentially with the number of lines ''n'' in the circuit. == Combinational ATPG ==

Automatic test pattern generation: Difference between revisions