FPGA prototyping: Difference between revisions

Revision as of 13:31, 27 November 2014

Revision as of 22:30, 25 November 2015

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A number of standard debugging tools are offered by FPGA vendors including ChipScope and SignalTAP. These tools can probe a maximum of 1024 signals and require extensive LUT and memory resources. For SoC and other designs, efficient debugging often requires concurrent access to 10,000 or more signals. If a bug is not able to be captured by the original set of probes, gaining access to additional signals results in a “go home for the day” situation. This is due to long and complex CAD flows for synthesis and place and route that can require from 8 to 18 hours to complete.

AnImproved improvedapproaches approachinclude istools thelike Certus tool from Tektronix<ref>{{cite web|url=http://www.eejournal.com/archives/articles/20121030-tektronix/ | title=Tektronix Shakes Up Prototyping, Embedded Instrumentation Boosts Boards to Emulator Status| publisher=Electronic Engineering Journal | date= 2012-10-30|accessdate=2012-10-30}}</ref> or thatEXOSTIV from Exostiv Labs<ref>{{cite web|url=http://www.design-reuse.com/news/38452/exostiv-labs-exostiv-fpga-debug.html | title=Exostiv Labs announces the availability of its 'EXOSTIV' solution for FPGA debug| publisher=Design & Reuse | date= 2015-10-14|accessdate=2015-11-25}}</ref>.

Certus brings fullenhanced RTL-level visibility to FPGA-based debugging. It uses a highly efficient multi-stage concentrator as the basis for its observation network to reduce the number of LUTs required per signal to increase the number of signals that can be probed in a given space. The ability to view any combination of signals is unique to Certus and breaks through one of the most critical prototyping bottlenecks.<ref>{{cite web|url=http://www.tek.com/document/whitepaper/break-through-your-asic-prototyping-bottlenecks | title=Break Through Your ASIC Prototyping Bottlenecks| date= 2012-10-23|accessdate=2012-10-30}}</ref>

EXOSTIV uses large external storage and gigabit transceivers to extract deep traces from FPGA running at speed. The improvement lays in its ability to see large traces in time as a continuous stream or in bursts. This enables exploring extended debugging scenarios that can't be reached by traditional embedded instrumentation techniques. The solution claims saving both the FPGA I/O resources and the FPGA memory at the expense of gigabit transceivers, for an improvement of a factor of 100,000 and more on visibility<ref>{{cite web|url=http://www.exostivlabs.com/why-exostiv/ | title=Why EXOSTIV?| date= 2015-10-14|accessdate=2015-11-25}}</ref>

==See also==