Power Processing Element: Difference between revisions

Revision as of 21:27, 2 December 2014

Revision as of 00:57, 4 December 2015

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== In-Order ==

{{main | Out-of-order execution}}

The PPU is an In-Order processor, but it has some unique traits which allow it to achieve some benefits of Out-of-Order execution without expensive re-ordering hardware. Upon reaching an L1 cache miss - it can execute past the cache miss, stopping only when an instruction is actually dependent on a load. It can send up to 8 load instructions to the L2 cache out-of-order. It also has an instruction delay pipe - a side path that allows it to execute instructions that would normally cause [[Bubble (computing)|pipeline stalls]] without holding up the rest of the [[Instruction pipeline|pipeline]]. The instruction delay pipeline is used for the Out-Of-Order Load/Stores: cache misses are put there while it moves on.

== Multithreading ==

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== Floating Point Capacity ==

Its [[64-bit]] [[SingleDouble-precision floating-point format|singledouble precision]] floating-point unit, and [[128-bit]] VMX unit (using the [[AltiVec]] instruction set), can perform a theoretical 12 floating-point operations per cycle, as all Power Architecture floating-point units can do floating-point multiply-adds, and come no smaller than 64-bits. That gives 3.2 billion clock cycles * 12 = 38.4 billion floating-point operations/second.

The PPU is enhanced in the [[Cell processor#PowerXCell 8i|PowerXCell 8i]] processor to be able to make single cycle [[Double-precision floating-point format|double precision floating point]] operations, tailored for high performance computing in supercomputers.