Power Processing Element: Difference between revisions

Revision as of 00:57, 4 December 2015

Revision as of 01:41, 4 December 2015

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== In-Order ==

{{main | Out-of-order execution}}

The PPU is an In-Order processor, but it has some unique traits which allow it to achieve some benefits of Out-of-Order execution without expensive re-ordering hardware. Upon reaching an L1 cache miss - it can execute past the cache miss, stopping only when an instruction is actually dependent on a load. It can send up to 8 load instructions to the L2 cache out-of-order. It also has an instruction delay pipe - a side path that allows it to execute instructions that would normally cause [[Bubble (computing)|pipeline stalls]] without holding up the rest of the [[Instruction pipeline|pipeline]]. The instruction delay pipeline is used for the Out-Of-Order Load/Stores: cache misses are put there while it moves on.

== The PPE's Pipeline ==

PPE has a 23 stage general pipeline with an additional 11 stages possible for Microcode and an additional 4 stages possible for Branch Prediction. <ref>[http://www.ibm.com/developerworks/library/pa-cellperf/ Cell Broadband Engine Architecture and its first implementation]</ref>

== Multithreading ==