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Fully-Buffered memory systems places a memory buffer device on every [[DIMM|memory module]] (called an [[FB-DIMM]] when Fully Buffered RAM is used), which unlike traditional memory controller devices, uses a serial data link to the memory controller instead of the parallel link used in previous RAM designs. This decreases the number of the wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory ___location). This increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB-DIMM controller, and back to a parallel form in the memory controller on the motherboard. In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for memory cell agnostic memory controller design, but this has not been demonstrated, as the technology is in its infancy.
As of [[2006]], most computers have a memory controller implemented on their motherboard's [[northbridge (computing)|north bridge]], though some modern [[microprocessors]], such as [[AMD]]'s Athlon 64, and [[Opteron]], [[IBM]]'s [[POWER5]], and [[Sun Microsystems]] [[UltraSPARC T1]] have a memory controller on the CPU die to reduce the [[memory latency]]. As this greatly increases the computer's performance, it locks the processor to that generation of memory, making the entire platform vulnerable to changes in memory technologies. This was witnessed in the shift to [[socket AM2]] on the Athlon 64 processor to allow the processor to use [[DDR2 SDRAM]].
== See also ==
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