Single instruction, multiple threads: Difference between revisions

Revision as of 23:18, 15 March 2015

Revision as of 18:52, 4 February 2016

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'''Single instruction, multiple thread''' (SIMT) is a [[parallel computing|parallel]] execution model, used in some [[GPGPU]] platforms, where [[Thread (computing)#Multithreading|multithreading]] is simulated by [[SIMD]] processors. The processors, say a number {{mvar|p}} of them, seem to execute many more than {{mvar|p}} tasks. This is achieved by each processor having multiple "threads" (or "work-items" or "[[Graphics_Core_Next#Compute_Units|Wavefronts]]"), which execute in lock-step, and are analogous to SIMD "lanes".<ref name="spp">{{cite book |author1=Michael McCool |author2=James Reinders |author3=Arch Robison |title=Structured Parallel Programming: Patterns for Efficient Computation |publisher=Elsevier |year=2013 |page=52}}</ref>

SIMT was introduced by [[Nvidia]]:<ref>{{cite web |url=http://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf |title=Nvidia Fermi Compute Arcitecture Whitepaper |date=2009 |website=http://www.nvidia.com/ |publisher=NVIDIA Corporation |accessdate=2014-07-17}}</ref><ref name=teslaPaper>{{cite web |url=http://dx.doi.org/10.1109/MM.2008.31 |title=NVIDIA Tesla: A Unified Graphics and Computing Architecture |date=2008 |website=http://www.ieee.org/ |publisher=IEEE |accessdate=2014-08-07 |page=6 {{subscription required|s}} }}</ref>