Flow to HDL: Difference between revisions

Revision as of 18:21, 17 January 2015

Revision as of 09:23, 21 February 2016

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{{unrefunreferenced|date=May 2012}}

'''Flow to HDL''' tools and methods convert flow-based system design into a [[hardware description language]] (HDL) such as [[VHDL]] or [[Verilog]]. Typically this is a method of creating designs for [[field-programmable gate array]], [[application-specific integrated circuit]] prototyping and [[digital signal processing]] (DSP) design. Flow-based system design is well-suited{{saysaccording whoto whom|date=May 2012}} to field-programmable gate array design as it is easier to specify the innate parallelism of the architecture.

== History==

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== See also ==

{{Commons category|Flow to HDL}}

* [[ASIC|Application Specific Integrated Circuit]] (ASIC)

* [[C to HDL]]