Content deleted Content added
No edit summary |
|||
Line 38:
=== Double data rate (DDR) SDRAM ===
[[DDR SDRAM|Double data rate (DDR) SDRAM]] is a later development of SDRAM. All types of SDRAM use a clock signal that is a square wave. This means that the clock alternates regularly between one voltage (low) and another (high), usually millions of times per second. Plain SDRAM, like most synchronous logic circuits, acts on the low-to-high transition of the clock and ignores the opposite transition. DDR SDRAM acts on both transitions, thereby halving the required clock rate for a given data transfer rate .
The DDR SDRAM standard is evolving, from DDR to [[DDR-2]] to DDR-3. At the time of writing (March 2004), DDR is the main memory standard. DDR-2 is expected to become the major standard in 2004/05, while DDR-3 is under development and standardization within [[JEDEC]] has started. The difference between DDR, DDR-2, DDR-3 is mostly in differing supply [[voltage]]s, different speed classes as well as some changes in the exact specification of the [[interface]].
| |||