Design for testing: Difference between revisions

Revision as of 19:07, 4 July 2006

Revision as of 18:49, 27 August 2006

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'''Design for Test''' (aka "Design for Testability" or "DFT") is a name for [[Integrated circuit design | design]] techniques that add certain testability features to a [[integrated circuit | microelectronic]] hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no defects that could adversely affect the product’s correct functioning.

Tests are applied at several steps in the [[Semiconductor fabrication|hardware manufacturing]] flow and, for certain products, may also be used for hardware maintenance in the customer’s environment. The tests generally are driven by [[Automated testing|test programs]] that execute in [[Automatic test equipment|Automatic Test Equipment]] (ATE) or, in the case of system maintenance, inside the assembled system itself. In addition to finding and indicating the presence of defects (i.e., the test fails), tests may be able to log [[diagnostic]] information about the nature of the encountered test fails. The diagnostic information can be used to locate the source of the failure.

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Depending on the DFT choices made during circuit design/implementation, the generation of Structural tests for complex logic circuits can be more or less [[Automatic test pattern generation|automated]]. One key objective of DFT methodologies, hence, is to allow designers to make trade-offs between the amount and type of DFT and the cost/benefit (time, effort, quality) of the test generation task.

== Looking forward ==

One challenge for the industry is keeping up with the [[Moore's law |rapid advances in chip technology]] (I/O count/size/placement/spacing, I/O speed, internal circuit count/speed/power, thermal control, etc.) without being forced to continually upgrade the test equipment. Modern DFT techniques, hence, have to offer options that allow next generation chips and assemblies to be tested on existing test equipment and/or reduce the requirements/cost for new test equipment. At the same time, DFT has to make sure that test times stay within certain bounds dictated by the cost target for the products under test.

== Diagnostics ==

Especially for advanced semiconductor technologies, it is expected some of the chips on each manufactured [[Wafer (electronics)|wafer]] contain defects that render them non-functional. The primary objective of testing is to find and separate those non-functional chips from the fully functional ones, meaning that one or more responses captured by the tester from a non-functional chip under test differ from the expected response. The percentage of chips that fail test, hence, should be closely related to the expected functional yield for that chip type. In reality, however, it is not uncommon that all chips of a new chip type arriving at the test floor for the first time fail (so called zero-yield situation). In that case, the chips have to go through a debug process that tries to identify the reason for the zero-yield situation. In other cases, the test fall-out (percentage of test fails) may be higher than expected/acceptable or fluctuate suddenly. Again, the chips have to be subjected to an analysis process to identify the reason for the excessive test fall-out.

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== References ==

''Electronic Design Automation For Integrated Circuits Handbook'', by Lavagno, Martin and Scheffer, ISBN 08493309630-8493-3096-3 A survey of the field of [[electronic design automation]]. This summary was derived (with permission) from Vol I, Chapter 21, ''Design For Test'', by Bernd Koenemann.

[[Category:Electronic design automation]]