Memory access pattern: Difference between revisions

Revision as of 21:38, 11 June 2016

Revision as of 21:39, 11 June 2016

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Sometimes reads and writes exhibit different access patterns. A series of random writes may [[scatter (vector addressing)|scatter]] data without needing to pull in cache lines, producing data that is easier to access sequentially in a subsequent step.

Alternatively an algorithm may randomly [[gather (vector addressing)|gather]] it's source data, whilst sequentially writing to it's destination. (thisThis foreknowledge can be exploited for parallelising, )and is usually preferable for [[GPU]] programming.