Memory access pattern: Difference between revisions

Revision as of 17:46, 14 June 2016

Revision as of 17:48, 14 June 2016

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{{Notability|date=June 2016}}

In [[computing]], a '''memory access pattern''' is the pattern with which a system or program reads and writes [[Memory (computing)|memory]]. These patterns differ in the level of [[locality of reference]] and drastically affect [[Cache (computing)|cache]] performance,<ref>{{cite web|title = data oriented design|url=http://www.dice.se/wp-content/uploads/2014/12/Introduction_to_Data-Oriented_Design.pdf}}</ref> and also have implications for the approach to [[parallelism (computing)|parallelism]] and distribution of workload in shared memory systems.

<ref>{{cite web|title=

Exploiting Memory Access Patterns to Improve Memory Performance in Data-Parallel Architectures|url=http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5473222&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5473222}}</ref>

<ref>{{cite web|title=Analysis of Energy and Performance of Code Transformations for PGAS-based Data Access Patterns|url=http://nic.uoregon.edu/pgas14/papers/pgas14_submission_17.pdf}}</ref>

<ref>{{cite web|title=xeon phi optimization|url=https://books.google.co.uk/books?id=DDpUCwAAQBAJ&pg=PA231&lpg=PA231&dq=scatter+memory+access+pattern&source=bl&ots=YiIyhx3udO&sig=QmwMzpNsEbVKma3YuC47Nq0nvmY&hl=en&sa=X&ved=0ahUKEwjo-ZzHv6XNAhXK1xQKHdvuAGYQ6AEILTAC#v=onepage&q=scatter%20memory%20access%20pattern&f=false}}</ref>

and distribution of workload in shared memory systems.

<ref>{{cite web|title=Analysis of Energy and Performance of Code Transformations for PGAS-based Data Access Patterns|url=http://nic.uoregon.edu/pgas14/papers/pgas14_submission_17.pdf}}</ref>

Further, [[cache coherency]] issues can affect multiprocessor performance

<ref>{{cite web|title=enhancing cache coherent architectures with memory access patterns for embedded many-core systems|url=http://www.cc.gatech.edu/~bader/papers/EnhancingCache-SoC12.pdf}}</ref>