Revision as of 17:48, 14 June 2016 edit Fmadd (talk \| contribs) Extended confirmed users 10,468 edits No edit summary ← Previous edit		Revision as of 17:48, 14 June 2016 edit undo Fmadd (talk \| contribs) Extended confirmed users 10,468 edits No edit summary Next edit →
Line 11: , which means that certain memory access patterns place a ceiling on parallelism (which [[manycore]] approaches seek to break ,<ref>{{cite web\|title=intel terascale\|url=https://cseweb.ucsd.edu/classes/fa12/cse291-c/talks/SCC-80-core-cern.pdf}}</ref> ).

Memory access pattern: Difference between revisions