Memory controller: Difference between revisions

Revision as of 18:05, 24 August 2006

Revision as of 11:39, 29 August 2006

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Reading and writing to DRAM is facilitated by use of [[multiplexer]]s and [[demultiplexer]]s, by selecting the correct row and column address as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM can select the correct memory ___location and return the data (once again passed through a multiplexer to reduce the number of wires necessary to assemble the system).

Bus width is the measure of how many parallel lanes of traffic are available to communicate with the memory cell. Memory controllers bus width ranges from [[8-bit]] in earlier systems, to 256-bit systems in more complicated systems and video cards (typically implemented as four, [[64-bit]] simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a [[128-bit]] memory device).

'''DualDouble Data Rate''' (DDR) memory controllers are used to drive [[DDR SDRAM]], where data is transfered on the rising and falling access of the memory clock of the system. DDR memory controllers are significantly more complicated than Single Data Rate controllers, but allow for twice the data to be transfered without increasing the clock rate or increasing the bus width to the memory cell.

'''[[Dual Channel]]''' memory controllers are memory controllers where the DRAM devices are separated onto two different busses to allow two memory controllers to access them in parallel. This doubles the theoretical amount of bandwidth of the bus. In theory, more channels can be built (a channel for every DRAM cell would be the ideal solution), but due to wire count, [[Crosstalk (electronics)|line capacitance]], and the need for parallel access lines to have identical lengths, more channels are very difficult to add.