Dynamic random-access memory: Difference between revisions

Revision as of 17:23, 5 November 2004

Revision as of 17:24, 5 November 2004

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[[Image:square_array_of_mosfet_cells_read.png|thumb|left|200px|Principle of operation of DRAM read, for simple 4 by 4 array.]]

[[Image:square_array_of_mosfet_cells_readsquare_array_of_mosfet_cells_write.png|thumb|right|200px|DRAM write]]

==Principle of operation of DRAM==

DRAM is usually arranged in a square array of capacitors (actually MOSFETs with big drain capacitances), as shown in the illustrations here which show a simple example with only 4 by 4 cells (more typical DRAM has 1024 by 1024 cells). During a read of any cell, the entire row is read out and written back in (refresh). During a write to a particular cell, the entire row is read out, one value changed, and then the entire row is written back in, as illustrated in the figure to the right.