Automatic test pattern generation: Difference between revisions

Revision as of 06:29, 19 December 2015

Revision as of 17:45, 14 August 2016

Line 1:

'''ATPG''' (acronym for both '''A'''utomatic '''T'''est '''P'''attern '''G'''eneration and '''A'''utomatic '''T'''est '''Pattern''' '''G'''enerator) is an [[electronic design automation]] method/technology used to find an input (or test) sequence that, when applied to a [[digital circuit]], enables [[automatic test equipment]] to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The generated patterns are used to test semiconductor devices after manufacture, and in some casesor to assist with determining the cause of failure ([[failure analysis]].<ref>{{cite conference| last=Crowell| first=G| author2=Press, R.| title=Using Scan Based Techniques for Fault Isolation in Logic Devices| booktitle=Microelectronics Failure Analysis | pages= 132–8}}</ref>) The effectiveness of ATPG is measured by the amountnumber of modeled defects, or [[fault models]], thatdetectable areand detected andby the number of generated patterns. These metrics generally indicate [[test quality]] (higher with more fault detections) and test application time (higher with more patterns). ATPG efficiency is another important consideration. Itthat is influenced by the fault model under consideration, the type of circuit under test ([[Scan chain|full scan]], synchronous sequential, or asynchronous sequential), the level of abstraction used to represent the circuit under test (gate, register-transfer, switch), and the required [[Fault coverage|test quality]].

== Basics of ATPG ==

A defect is an error caused in a device during the manufacturing process. A fault model is a mathematical description of how a defect alters design behavior. The logic values observed at the device's primary outputs, while applying a test pattern to some device under test (DUT), are called the output of that test pattern. The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern. A fault is said to be ''detected'' by a test pattern if the output of that test pattern, when testing a device that has only that one fault, is different than the expected output. The ATPG process for a targeted fault consists of two phases: ''fault activation'' and ''fault propagation''. Fault activation establishes a signal value at the fault model site that is opposite of the value produced by the fault model. Fault propagation moves the resulting signal value, or fault effect, forward by sensitizing a path from the fault site to a primary output.

ATPG can fail to find a test for a particular fault in at least two cases. First, the fault may be intrinsically undetectable, such that no patterns exist that can detect that particular fault. The classic example of this is a redundant circuit, designed sosuch that no single fault causes the output to change. In such a circuit, any single fault will be inherently undetectable.

Second, it is possible that a detection pattern(s) existexists, but the algorithm cannot find itone. Since the ATPG problem is [[NP-complete]] (by reduction from the [[Boolean satisfiability problem]]) there will be cases where patterns exist, but ATPG gives up sinceas it will take an incrediblytoo long time to find them (assuming [[P = NP problem|P≠NP]], of course).

== Fault models ==

Line 14:

=== Fault collapsing ===

It is possible that Two or moreEquivalent faults, produce the same faulty behavior for all input patterns. these faults are called equivalent faults. Any single fault from the set of equivalent faults can represent the whole set. In this case, much less than ''k×n'' fault tests are required for a circuit with ''n'' signal line. Removing equivalent faults from entire set of faults is called fault collapsing.

==== The Stuck-at fault model ====

{{main|Stuck-at fault}}

In the past several decades, the most popular fault model used in practice is the single [[stuck-at fault]] model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. Hence, if a circuit has ''n'' signal lines, there are potentially ''2n'' stuck-at faults defined on the circuit, of which some can be viewed as being equivalent to others. The stuck-at fault model is a ''logical'' fault model because no delay information is associated with the fault definition. It is also called a ''permanent'' fault model because the faulty effect is assumed to be permanent, in contrast to ''intermittent'' faults which occur (seemingly) at random and ''transient'' faults which occur sporadically, perhaps depending on operating conditions (e.g. temperature, power supply voltage) or on the data values (high or low voltage states) on surrounding signal lines. The single stuck-at fault model is ''structural'' because it is defined based on a structural gate-level circuit model.

A pattern set with 100% stuck-at fault coverage consists of tests to detect every possible stuck-at fault in a circuit. 100% stuck-at fault coverage does not necessarily guarantee high quality, since faults of many other kinds—suchkinds asoften occur (e.g. bridging faults, opens faults, anddelay transition (aka delayfaults) faults—often occur.

==== Transistor faults ====